Design Analysis of 128-bit Adder/Subtractor using Manchester Carry Chain

Question 1 (70 marks)

In Week 5, you learned about adders and the Manchester carry chain (MC2), which is used to speed up the propagation of the carry signal in the carry-bypass and carry-select adders. For this question, you will analyze the design of an adder/subtractor that takes as inputs two 128-bit signed integers (A and B) and generates an output that is 129-bit wide (128 sum bits plus the final carry-out). For this question, assume that:
 

i) Complementary signals are available for all input bits to the 128-bit adder/subtractor (the carry-in at the LSB and all the bits of the inputs A and B), and

ii) The channel length, L, of the MOSFETs cannot be changed. Submit a report for the analysis you will be doing for this question. Clearly state all

Since all carry-bits are determined by the MC2, the 128-bit adder/subtractor can be built by adding to the MC2 the sum signal logic circuit in the mirror adder (see Figure Q1-2) that can generate all the individual sum bits.

(a) Assuming the MC2 that is available is as shown in Figure Q2-1. Draw the schematic of the sum signal logic gate, modified from that in Figure

Q1-2, that will give the correct sum bits from the MC2 in Figure Q2-1. To save on area and power consumption, ensure your circuit has the fewest additional inverters.

(b) Write down the (W/L) ratios of all NMOS and PMOS transistors in the sum signal logic gate from Q2(a) so that the worst-case resistance of the PDN is the same as the ON resistance between the source and drain of an NMOS transistor that has (W/L)N = 4, and the worst-case resistance of the PUN is the same as the ON resistance between the source and drain of a PMOS transistor that has (W/L)P = 8.

(c) The capacitor model for the MOSFET is shown in Figure Q2-2 for this question. You are given that C_NI and C_PI are directly proportional to (W/L) of the corresponding transistor, and when (W/L)N = 1 = (W/L)P, C_NI = C_PI and C_GN = C_GP = 10 C_NI. If (W/L)N = 1 and (W/L)P = 2 for the transistors in the MC2, what are the effective capacitances at the carry nodes for all bit positions of the 128-bit adder/subtractor (from the carry-in to the LSB all the way to the carry-out of the MSB) that is built by connecting the MC2 in Q2-1 with the sum signal logic gates in Q2(b)?

Figure Q2-2. The capacitance models for the MOSFETs may be simplified so that only three capacitors instead of five capacitors need to be included.

(d) In class, we learned that the delay of the pass transistor logic gate scales as N2, where N is the number of series connected transistors. One technique that can help to alleviate this design issue is to insert buffers as shown in Figure Q2-3. The sum signal logic gate in Figure Q1-2 can be used for the part of the MC2 where the carries are active high, and the sum signal logic gate for Q2(a) can be used for the part of the MC2 where the carries are active low.

Draw the schematic of the sum signal logic gate to be used with the part of the MC2 where the carriers are active high, and give the sizes of the transistors in the logic gate according to the same sizing rules as in Q2(b). Figure Q2-3. The MC2 in Figure Q2-1 is partitioned into to stages covering 3-bits in each stage. A static CMOS inverter is inserted to interface the two stages of the MC2.

(e) Based on the results from Q2(c) and (d), what are the effective capacitances at all the carry nodes for all bit positions if the MC2 used in the 128-bit adder/subtractor has two stages (64-bits per stage)? In your answer, include an additional load capacitance for the carry-out of the MSB of the adder/subtractor.

(f) We will now analyze the critical path delay of the staged design of the Manchester carry chain based on the model you develop in Q2(d). As clearly seen in Figure Q2-3, consecutive stages of the buffered MC2 will alternate between active high and active low carry signals. Calculate the critical path delays of the staged MC2 design with different number of bits per stage and clearly show whether the number of bits per stage of the MC2 can be adjusted to minimize the critical path delay. In this analysis, consider only cases where the number of bits per stage is a power of two (i.e., 2, 4, 8, 16, 32, 64, 12.