Design and Test Simple 8-bit Microprocessor (SMP8)

Objective: Design and test a simple 8-bit Microprocessor (SMP8). 
Given: Instruction set : description of instructions, formats, opcodes, type of on-chip memories, type and number of registers. Design hints. Also refer to a single-cycle MIPS design. 

I. Description 

The SMP8 is an 8-bit processor (instructions and data are 8-bit length). SMP8 has one 8-bit general purpose register, R, and an 8-bit Accumulator Register, AC. The result of arithmetic operation is to be automatically loaded into AC register. One of the operands in two-operand arithmetic/logic instructions (ADD, SUB, XOR, OR, AND) is always supplied from AC, and another comes from R register. There is 1-bit flip-flop, Zero flag, Z. It is set to 1, if the result of any arithmetic or logic instruction is 0. Otherwise, it is 0. This is to be done automatically by hardware. There is also PC- program counter to form the instruction address. Both Data and Instruction memories are 16x 1 byte (toy) memories.

Conditional Branch instructions are JMPZ (if FlagZ=1) and JMPNZ (if Flag Z=0). Unconditional branch is JUMP. Memory Load and Store are implemented with Accumulator: LDAC instruction reads from Data Memory into AC, and STAC writes the contents of AC into the Data Memory. There is only one type of memory addressing: direct (absolute). There are two instructions to move data from and to Accumulator: MVAC (From AC to R) and MOVR (from R to AC). Increment (INAC) and NOT are performed on the operand that comes from AC register and the result goes back to Accumulator. Clear Accumulator (CLAC) sets Accumulator to 0. NOP does nothing (void).

II. Assignment 
1. Design the microprocessor (datapath and control unit). 
a. The simplicity of the processor suggests a single cycle implementation. So, follow that path of design. 
b. PC is to be incremented using an increment circuit. You can merge PC register and up-counter. At Start and Reset, PC is to be set to 0. 
c. Start with the datapath design: design ALU, and then add all other components. 
d. Designate control signals required for Datapath operation. That includes multiplexers for selecting inputs or outputs, Clock gating signals for loading data into registers. Z flip-flop is to be updated every time AC register is getting data in. 
e. Create the control word table. 
f. Design the control unit. Opcode decoder (4-to-16) is a major part of it. The control unit is purely combinational circuit. 
g. Design on-chip memories of indicated depth/width.

2. Print out the ALU, complete datapath and the control unit circuits using RTL viewer. 
3. For the test code 1 below write the machine code and .dat files for both instruction and data memory initialization. 
4. Write a testbench for testing your design. For test code 1, you have to check if the memory address in Line 7 is 2 and data to write into that address is 114. 
5. Repeat p. 3 for Test code 2; initialize memory with all zeroes. Calculate what would be written into Data memory at address 4, and include this into the testbench. 
6. Using Timequest, obtain the correct Clock value and calculate how long it takes to complete Test code 1 and test code 2.

7. Submit .v and .dat files of your project and the snapshots of the ModelSim simulation outcomes separately for test code 1 and test code 2.

III. Test codes and Data Memory contents to initialize and test 
Test code 1 ( Instruction Memory ) 
0: LDAC 0 
1: INAC 
2: JPNZ 4 
3: JUMP 0 
4: INAC 
5: MVAC 
6: ADD 
7: STAC 2 
8: NOP

Test Code 2 (Instruction Memory) 
0: CLAC 
1: INAC 
2: MVAC 
3: NOT 
4: XOR

5: JMPZ 10 
6: STAC 4 
7: NOP 
8: NOP 

IV. DELIVERABLE 
1. RTL viewer for ALU, Datapath and Control unit, all three, separately. 
2. Control word table for the control unit. 
3. Verilog Code, .dat file and testbench code (for test code 1 and 2) 
4. ModelSim simulation screenshots (waveform and console), should include in hex and clear operation of each executed instructions. 
5. Clock calculation report supported by TimeQuest display screen shot confirming that there is no negative slack and the positive slack in 10% of the clock (not more than that). 
6. Submit zip v. files. 
7.  Demo on a DE2 board, with the content of AC on the leds